【教程】 Reset Release IP 的介绍与使用

本文介绍参考Altera的文档：Device Configuration User Guide Agilex™ 5 FPGAs and SoCs 

https://docs.altera.com/viewer/book-attachment/XbjAQgz2d1lAcDGafRnL0A/RGB4FFvfEylqY9dyWb450A-XbjAQgz2d1lAcDGafRnL0A

 

 

 

Critical Warning(20759): Use the Reset Release IP in Intel Agilex 3 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide.